Efficient Implementation of Digital Receiver on FPGA
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

Efficient Implementation of Digital Receiver on FPGA

M. Sravani, B. Madhavi

There is a boast demand for wireless communication technology in present days. All the new wireless technologies are communicated by the Digital receiver. The main aim of this receiver is obtain information from target devices, after receiving information the parameters like speed, distance and angle of target device are calculated in Radars. In this paper introduced a 70 MHz Digital receiver which has high sampling rate for narrow band as well as wide band digital signals. The main key components of this digital receiver are DDC (Digital Down Converter) for frequency translation and ADC interface Unit to convert double rate data in to single rate data (7 bit double rate in to 14 bit single rate data). This receiver has more stability and higher precision of the signal than analogue counterparts. The Architecture of digital receiver implemented on FPGA.

Keywords: Digital Receiver, Digital down converter, RADAR, FMC daughter card

Edition: Volume 4 Issue 6, June 2015

Pages: 2835 - 2838

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How to Cite this Article?

M. Sravani, B. Madhavi, "Efficient Implementation of Digital Receiver on FPGA", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB156115, Volume 4 Issue 6, June 2015, 2835 - 2838

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