Abstract of Low Noise & High Speed Domino Logic Circuit
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064

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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

Low Noise & High Speed Domino Logic Circuit

Reetu Narayan, Kumar Saurabh

Dynamic logic style is used in high performance circuit designs due to its high speed. But during cascading of dynamic gates, problem arises due to charge sharing, charge redistribution and charge leakage. To avoid these problems, domino logic design is used in the circuit due to their advantages such as their high speed and less noise immunity. In this paper we have proposed a new domino circuit which has very small speed power product as compared to previous designs of domino logic circuits. Simulation are carried out for 90nm technology with Vdd = 1 Volt, for the case of OR gate.

Keywords: Domino logic, Dynamic Logic, Diode Footed Logic, Pull down Network, Pull up network, Charge sharing, charge leakage

Edition: Volume 4 Issue 6, June 2015

Pages: 3016 - 3021

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How to Cite this Article?

Reetu Narayan, Kumar Saurabh, "Low Noise & High Speed Domino Logic Circuit", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB156004, Volume 4 Issue 6, June 2015, 3016 - 3021

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