International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064



M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic

Amol D. Rewatkar, R. N. Mandavgane, S. R. Vaidya

Adders are the basic functional unit of arithmetic operations. Due to the quickly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The CMOS carry select adder (CSLA) consists of two sets of ripple carry adder (RCA) and the modified CSLA replaces one set of RCA with a binary to Excess One (BEC) converter. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper presents a performance analysis of reversible, VLSI implementations of 16 bit carry select adders suitable for multi-digit addition. The Reversible logic (RVL) provides the key benefit of a higher data processing capability per unit chip area. This paper present design of 16 bit CSLA using Tanner EDA tool & simulated using T-spice simulator. With the help of Reversible technique 16 bit Reversible Carry Select Adder has been proposed in these paper. The Proposed CSLA has reduced transistor count as well as power consumption as that of CMOS CSLA.

Keywords: Area Efficient, CSLA, Low Power, BEC

Edition: Volume 4 Issue 6, June 2015

Pages: 2737 - 2741


How to Cite this Article?

Amol D. Rewatkar, R. N. Mandavgane, S. R. Vaidya, "A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155997, Volume 4 Issue 6, June 2015, 2737 - 2741

22 PDF Views | 20 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Area Efficient'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2737 - 2741

A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic

Amol D. Rewatkar, R. N. Mandavgane, S. R. Vaidya

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 798 - 802

Modified Booth Multiplier with FIR Filter

B. Sireesha, Diana Aloshius

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 1699 - 1704

Algebraic Integer based 2-D DCT Computation using Single Channel Architecture

B. Uday, P. Apsar

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2519 - 2526

Efficient Implementation of Reconfigurable MIMO Decoder Architecture

Teena Philip, S. Suresh Babu

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 2700 - 2704

Design and Verification of Truncation-Error-Tolerant 8 Bit Signed-Multiplier

Shruti Verma, Rakesh Jain

Share this article



Similar Articles with Keyword 'CSLA'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2737 - 2741

A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic

Amol D. Rewatkar, R. N. Mandavgane, S. R. Vaidya

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2997 - 3000

Area Efficient architecture for 64 bit CSLA using Sum and Carry Generation Unit

Mahadev Bobade, M. N. Kakatkar

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 8 Issue 11, November 2019

Pages: 964 - 967

Low Power and Area Efficient Carry Select Adder Using D-Flip Flop

S. Muminthaj, S. Kayalvizhi, K. Sangeetha

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 2, February 2016

Pages: 1444 - 1447

An Efficient Architecture of Carry Select Adder Using Logic Formulation

Kaveri.N, Senthil Kumar.P

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015

Pages: 344 - 347

Area Optimized Double Precision IEEE Floating Point Adder

Elizabeth Joseph Mattam, Deepa Balakrishnan

Share this article



Similar Articles with Keyword 'Low Power'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 5, May 2016

Pages: 2286 - 2288

Realization of Programmable PRPG with Enhanced Fault Coverage Gradient

Lakshmi Asokan, Jeena Maria Cherian

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2218 - 2222

A Power Efficient Design of Reversible RAM Using Pseudo Reed-Muller Expression

Shibinu A. R, Rajkumar.P

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 1332 - 1335

Low Power Self-Timed TCAM Based on Overlapped Search Mechanism with IP Filter Implementation

Jerrin Paul M, Hazel Elsa John

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015

Pages: 2335 - 2340

Analysis of Design of Schmitt Trigger Based SRAM Cell Using a Novel Power Reduction Technique

J. Madhuri, S. Anitha

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 4, April 2013

Pages: 157 - 159

Interfacing between High Performance Drivers and Low Power Devices using ABP Bridge

N. Sudhakar, M. Kiran Kumar

Share this article



Similar Articles with Keyword 'BEC'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 1842 - 1847

A Novel Mac Based Congestion Control System for VANET with Adaptive Routing

Mahanthgouda, Sridhara. K

Share this article

Survey Paper, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2359 - 2361

Ambient Energy Sources, Applications and Ambient Energy Harvesting in Cognitive Radio

Aparna Singh, Anu Shrivastava

Share this article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 866 - 868

Design and Implementation of Efficient FSM for AHB Master and Arbiter

Muzammel Hoque, Owais Shah

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 2703 - 2707

Introduction to Multiple Beams Adaptive Linear Array Using Genetic Algorithm

Ummul Khair Maria Roohi

Share this article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 2466 - 2468

Review on Hardware-in-Loop Simulation used to Advance Design Efficiency and Test Competency

Prajakta Patil, Snehal Bhosale

Share this article
Top