A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic

Amol D. Rewatkar, R. N. Mandavgane, S. R. Vaidya

Adders are the basic functional unit of arithmetic operations. Due to the quickly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The CMOS carry select adder (CSLA) consists of two sets of ripple carry adder (RCA) and the modified CSLA replaces one set of RCA with a binary to Excess One (BEC) converter. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper presents a performance analysis of reversible, VLSI implementations of 16 bit carry select adders suitable for multi-digit addition. The Reversible logic (RVL) provides the key benefit of a higher data processing capability per unit chip area. This paper present design of 16 bit CSLA using Tanner EDA tool & simulated using T-spice simulator. With the help of Reversible technique 16 bit Reversible Carry Select Adder has been proposed in these paper. The Proposed CSLA has reduced transistor count as well as power consumption as that of CMOS CSLA.

Keywords: Area Efficient, CSLA, Low Power, BEC

Edition: Volume 4 Issue 6, June 2015

Pages: 2737 - 2741

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How to Cite this Article?

Amol D. Rewatkar, R. N. Mandavgane, S. R. Vaidya, "A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155997, Volume 4 Issue 6, June 2015, 2737 - 2741

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