Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015
Analysis of Modified Hybrid Full Adder with High Speed
Abstract: In digital CMOS design, power consumption has been a major concern for several years advanced IC fabrication technology allows the use of nano-scale devices so inability to get power to circuits, power leakage or to remove the heat they generate. By optimizing the transistor size in each stage power and delay can be minimized. This paper presents the analysis of full adders having efficient parameters like PDP, power, delay by mean of power consumption and speed. These full adders were designed by various designs. Although these full adders were more efficient and better than the standard full adder but these adders are stimulated using 90nm, 180nm CMOS technologies by using various tools like TSPICE tool, cadence virtuoso, and synopsis. This purposed circuit reports with better performance parameters like low delay (213.78 ps), high speed better PDP (0.642fj) with lesser power consumption (3.007W) at 180nm CMOS technology using TPL (transmission pass logic) and CMOS (complementary metal oxide semiconductor) logic designs. The circuit is first implemented at 1bit full adder and then extended to 32 bit ripple carry adder also on tanner EDA tool.
Keywords: advanced VLSI, TPL, High speed, full adder, PDP, CMOS, ALU, RCA
Edition: Volume 4 Issue 6, June 2015,
Pages: 2827 - 2831
How to Cite this Article?
Jigyasa, Kumar Saurabh, "Analysis of Modified Hybrid Full Adder with High Speed", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SUB155939, Volume 4 Issue 6, June 2015, 2827 - 2831, #ijsrnet
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