Analysis of Low Power Pulse Triggered Flip Flop
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

Analysis of Low Power Pulse Triggered Flip Flop

Deepika Goyal

Flip Flops are critical timing elements in digital systems which has large impact on circuit speed and power consumption. The performance of flip flop is an important parameter to determine performance of whole synchronous circuit. In this paper, comparison of existing flip flops with different parameters is calculated. A new design a low power pulse triggered flip-flop (FF) has been proposed having a structure of explicit pulse triggered flip flop with a modified true phase single latch based on single feed through scheme. Pulse Triggered FF has a simple circuit which lowers the power consumption. The simulation is done on TANNER EDA using 90nm technology which verifies that Setup time, Hold time, D to Q delay, Average Power and optimal PDP has been reduced when compared with existing systems. P-FF gives a higher toggle rate for high-speed operations. The flip flop has shortened the delay, power etc which improves the speed, efficiency and power of the system.

Keywords: Flip Flop FF, low power pulse triggered flip flop, explicit pulse data close to output ep-DCO

Edition: Volume 4 Issue 6, June 2015

Pages: 2799 - 2802

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How to Cite this Article?

Deepika Goyal, "Analysis of Low Power Pulse Triggered Flip Flop", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155808, Volume 4 Issue 6, June 2015, 2799 - 2802

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