A Hierarchical Design of 32-bit Vedic Multiplier
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

A Hierarchical Design of 32-bit Vedic Multiplier

Arpita S. Likhitkar, M. N. Thakare, S. R. Vaidya

Many processor devotes a considerable amount of processing time in performing arithmetic operations particularly multiplication operations therefore high-speed multiplier is much desired. There are various methods of multiplication in Vedic mathe-matics, Urdhva tiryagbhyam, being a general multiplication formula is equally applicable to all cases of multiplication. This is more efficient in the multiplication of large numbers with respect to speed and area. In that we will see the different types of multiplier that will be generated using a Vedic Mathematics. In that we will proposed a 4-bit binary multiplier using this sutra. A new 4-bit adder is proposed which when used in multiplier,. Also we proposed 8-bit adder, 16 bit adder & 32 bit adder using this adder we proposed an 8-bit multiplier, 16 bit multiplier & 32 bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) for generating the partial products. Also this paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics.

Keywords: VLSI, Urdhva Tiryagbhyam sutra, Adder, Multiplier

Edition: Volume 4 Issue 6, June 2015

Pages: 1321 - 1324

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How to Cite this Article?

Arpita S. Likhitkar, M. N. Thakare, S. R. Vaidya, "A Hierarchical Design of 32-bit Vedic Multiplier", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155553, Volume 4 Issue 6, June 2015, 1321 - 1324

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