International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




Downloads: 119

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015


Design and Implementation of FIR filter using Carry Select Adder

Ashwini A. Lokhande [2] | V. G. Raut


Abstract: Carry Select Adder (CSLA) is a basic building blocks used in data processing processor to carry out fast arithmetic functions. As a scale of integration keeps growing, signal processing systems is being implemented on a VLSI chip to a greater extent which demand not only high computation capacity but also consume large amount of energy. While performance and area remain to be the two major design parameters, power consumption is become a critical task in today-s VLSI system design. To reduce the power consumption of data processing processor we need to reduce number of transistors of the adder. So, there is a chance to reduce the power and delay in the CSLA structure. The proposed design uses D-latch instead of using RCA cascade structure for cin=1or cin=0. This CSLA is implemented in the adder of FIR filter. The proposed design achieves the two folded advantages in terms of delay and power.


Keywords: CSLA, RCA, D-Latch, low power, high speed


Edition: Volume 4 Issue 6, June 2015,


Pages: 1399 - 1402

Design and Implementation of FIR filter using Carry Select Adder


How to Cite this Article?

Ashwini A. Lokhande, V. G. Raut, "Design and Implementation of FIR filter using Carry Select Adder", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SUB155544, Volume 4 Issue 6, June 2015, 1399 - 1402, #ijsrnet

How to Share this Article?

Enter Your Email Address




Similar Articles with Keyword 'CSLA'

Downloads: 106

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 2242 - 2245

Design and Implementation of 64-Bit Multiplier Using CLAA and CSLA

Shaik Meerabi | Krishna Prasad Satamraju

Share this Article

Downloads: 112

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2997 - 3000

Area Efficient architecture for 64 bit CSLA using Sum and Carry Generation Unit

Mahadev Bobade | M. N. Kakatkar

Share this Article


Top