Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors

Deepak Kurmi, V. B. Baru

Multiplier unit is the key block of digital signal processors as well as general purpose processors that substantially decide the speed of processor. Design of high speed multiplier is need of the day. This paper introduces a high speed multiplier architecture using Vedic mathematics Urdhwa-Tiryakbhyam sutra, however speed of multiplier greatly depends upon the addition of partial products. To further increase the speed of multiplier a novel approach of 42 and 72 compressors has been used, these compressors are very efficient in terms of speed of addition and require lower gate count. Vedic mathematics, compressors and reconfigurable multiplication architecture has been used to implement high speed 32 bit multiplier. The delay of 32 bit proposed multiplier is 44.249 ns. Upon comparison, the proposed multiplier is 1.5 times faster than existing Vedic multiplier and almost 2 times faster than conventional and booth multiplier. The architecture has been implemented using Verilog language and the tool used for simulation is Xilinx ISE 14.5.

Keywords: VLSI, FPGA, Compressors, Vedic Mathematics

Edition: Volume 4 Issue 6, June 2015

Pages: 1527 - 1531

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How to Cite this Article?

Deepak Kurmi, V. B. Baru, "Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155526, Volume 4 Issue 6, June 2015, 1527 - 1531

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