Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015
High Speed Vedic Multiplier Design Based On CSLA
Sijo Mathew | S. Chinnapparaj | Dr. D. Somasundareswari
Abstract: This work proposes an high speed Vedic Multiplier based on area, delay and power efficient Carry Select Adder. In this paper a fast method of multiplication based on ancient Indian Vedic mathematics is proposed. The whole of Vedic mathematics is based on 16 sutras and manifests a unified structure of mathematics. Among the various methods of multiplication in Vedic mathematics, Urdhava tiryakbhyam is discussed in detail. All the redundant logic operations present in the conventional CSLA are eliminated and proposed a new logic formulation for CSLA. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. The multiplier discussed here is compared with other multiplier to highlight the speed and power superiority of the vedic multiplier.
Keywords: Carry Select Adder, Urdhava Tiryakbhyam Sutra, Multiplier, Vedic Mathematics, Low power design
Edition: Volume 4 Issue 6, June 2015,
Pages: 1068 - 1072
How to Cite this Article?
Sijo Mathew, S. Chinnapparaj, Dr. D. Somasundareswari, "High Speed Vedic Multiplier Design Based On CSLA", International Journal of Science and Research (IJSR), Volume 4 Issue 6, June 2015, pp. 1068-1072, https://www.ijsr.net/get_abstract.php?paper_id=SUB155431
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