ASIC Architectures for Implementing ECC Arithmetic over Finite Fields
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Views: 127 , Downloads: 100 | CTR: 79 % | Weekly Popularity: ⮙1

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

ASIC Architectures for Implementing ECC Arithmetic over Finite Fields

Hemanth Ravindra, Jalaja S

The ever growing need for improved security for applications over internet has resulted in wide acceptance of Elliptic Curve Cryptography (ECC) in industry and academic research. This growth has started the spread of architectures for implementing ECC from FPGA towards ASIC. Computing scalar multiplication and point inversion forms the core ECC architecture. This paper discusses the ASIC based implementation of these ECC arithmetic primitives over finite fields GF (2m). Scalar multiplication is based on a recursive variant of Karatsuba Algorithm and Inversion algorithms are based on quad-ITA. The arithmetic components are designed using Verilog and implemented using Cadence 45nm fast technology library. The proposed variation of Karatsuba Multiplier has low power considerations and better area delay product.

Keywords: ASIC based ECC, Karatsuba Algorithm variations, Combination of Algorithms, Quad-ITA, Low power design

Edition: Volume 4 Issue 6, June 2015

Pages: 878 - 884

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How to Cite this Article?

Hemanth Ravindra, Jalaja S, "ASIC Architectures for Implementing ECC Arithmetic over Finite Fields", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155280, Volume 4 Issue 6, June 2015, 878 - 884

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