A Review: Design and Simulation of Binary Floating Point Multiplier Using VHDL
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Review Papers | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

A Review: Design and Simulation of Binary Floating Point Multiplier Using VHDL

Ujjwala V. Chaudhari, Prof A. P. Dhande

Most of the DSP applications need floating point numbers multiplication. The possible ways to represent real numbers in binary format floating point numbers are, the IEEE 754 standard represents two floating point formats, Binary interchange format and Decimal interchange format. To improve speed multiplication of mantissa is done using specific multiplier replacing Carry Save Multiplier. To give more precision, rounding is not implemented for mantissa multiplication. The binary floating point multiplier is plane to do implemented using VHDL and it is simulated and synthesized by using ModelSim and Xilinx ISE software respectively. The result so got will be compare with the previous work done. Floating point multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting.

Keywords: floating point, ModelSim, Xilinx ISE, Binary interchange format, Decimal interchange format

Edition: Volume 4 Issue 6, June 2015

Pages: 169 - 171

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How to Cite this Article?

Ujjwala V. Chaudhari, Prof A. P. Dhande, "A Review: Design and Simulation of Binary Floating Point Multiplier Using VHDL", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155127, Volume 4 Issue 6, June 2015, 169 - 171

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