Asymmetric SRAM Memory Cell for Power Reduction
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Review Papers | Electronics & Communication Engineering | India | Volume 4 Issue 5, May 2015

Asymmetric SRAM Memory Cell for Power Reduction

Elizebeth Mohan, Sarabdeep Singh

The main objective of this paper is to present the reasons for the preference of asymmetric SRAM cell over symmetric SRAM for cache memory applications. Since memory is main and consists a large part of systems, nearly fifty percent, reducing the power and delay in memories have become a hot burning issue. Almost half of the total CPU (central processing unit) dissipation is due to memory operations. SRAM memory is an essential building block for all processors and VLSI systems. Ideally, a SRAM cell should be fast and should dissipate low leakage power. Traditional SRAM cells are symmetrically composed of transistors with identical leakage and threshold characteristics, whereas asymmetric SRAM cell designs offer low leakage with little or no impact on latency.

Keywords: SRAM, Low-leakage, Low-power, Dual-Vt

Edition: Volume 4 Issue 5, May 2015

Pages: 2990 - 2992

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How to Cite this Article?

Elizebeth Mohan, Sarabdeep Singh, "Asymmetric SRAM Memory Cell for Power Reduction", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155015, Volume 4 Issue 5, May 2015, 2990 - 2992

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