International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Double Blind Reviewed

ISSN: 2319-7064




Downloads: 107

Research Proposals or Synopsis | Electronics & Communication Engineering | India | Volume 4 Issue 5, May 2015


An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits

Avinash Singh [2] | Dr. Subodh Wairya


Abstract: This paper presents the design of low power and high speed circuit using a new CMOS logic family called feedthrough logic. FTL arithmetic circuits provides for smaller propagation time delay when compared with the standard CMOS technologies. The proposed circuit has very low dynamic power consumption and lower propagation delay compared to the recently proposed circuit techniques for the dynamic logic styles. A long chain of inverters (20 stages) and a 16-bit ripple carry adder (RCA) is designed by modified feedthrough logic. Then comparison analysis has been carried out by simulating the circuitry in 180nm CMOS process technology from TSMC using Tanner EDA 14.11 tool.


Keywords: Feedthrough logic FTL, high speed, low power adder, CMOS logic circuit


Edition: Volume 4 Issue 5, May 2015,


Pages: 2277 - 2280


How to Cite this Article?

Avinash Singh, Dr. Subodh Wairya, "An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits", International Journal of Science and Research (IJSR), Volume 4 Issue 5, May 2015, pp. 2277-2280, https://www.ijsr.net/get_abstract.php?paper_id=SUB154783

How to Share this Article?






Similar Articles with Keyword 'high speed'

Downloads: 0

Analysis Study Research Paper, Electronics & Communication Engineering, India, Volume 11 Issue 11, November 2022

Pages: 966 - 969

High Speed Low Power 8-Bit Binary up Counter in 45nm CMOS Technology

S. Sivashankari

Share this Article

Downloads: 2 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Student Project, Electronics & Communication Engineering, India, Volume 10 Issue 9, September 2021

Pages: 122 - 125

Design of 256 x 256 bit Vedic Multiplier

Aishwarya K M | Dr. Kiran V [3]

Share this Article


Top