Research Proposals or Synopsis | Electronics & Communication Engineering | India | Volume 4 Issue 5, May 2015
An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits
Avinash Singh  | Dr. Subodh Wairya
Abstract: This paper presents the design of low power and high speed circuit using a new CMOS logic family called feedthrough logic. FTL arithmetic circuits provides for smaller propagation time delay when compared with the standard CMOS technologies. The proposed circuit has very low dynamic power consumption and lower propagation delay compared to the recently proposed circuit techniques for the dynamic logic styles. A long chain of inverters (20 stages) and a 16-bit ripple carry adder (RCA) is designed by modified feedthrough logic. Then comparison analysis has been carried out by simulating the circuitry in 180nm CMOS process technology from TSMC using Tanner EDA 14.11 tool.
Keywords: Feedthrough logic FTL, high speed, low power adder, CMOS logic circuit
Edition: Volume 4 Issue 5, May 2015,
Pages: 2277 - 2280
How to Cite this Article?
Avinash Singh, Dr. Subodh Wairya, "An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits", International Journal of Science and Research (IJSR), Volume 4 Issue 5, May 2015, pp. 2277-2280, https://www.ijsr.net/get_abstract.php?paper_id=SUB154783
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