International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064


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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 5, May 2015


Implementation of Decimal Matrix Code For Multiple Cell Upsets in Memory

Shwetha N, Shambhavi S


Abstract: Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would Require higher delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not improved in all cases. In this paper, novel decimal matrix code (DMC) based on divide-symbol is proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. Moreover, the encoder-reuse technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The proposed DMC is compared to well-known codes such as the existing Hamming, MCs, and punctured difference set (PDS) codes.


Keywords: Decimal algorithm, error correction codes ECCs, mean time to failure MTTF, memory, multiple cells upsets MCUs


Edition: Volume 4 Issue 5, May 2015,


Pages: 1503 - 1509


How to Cite this Article?

Shwetha N, Shambhavi S, "Implementation of Decimal Matrix Code For Multiple Cell Upsets in Memory", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SUB154502, Volume 4 Issue 5, May 2015, 1503 - 1509

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