M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015
Low Power FPGA Architecture
Abhijeet Khandale | Dr. H R Bhagyalakshmi
Abstract: A comprehensive analysis and implementation of FPGA architecture for low routing power and clock gated CLBs has been presented in this paper. The power consumption in FPGAs is more in routing and in clock network. As the FPGA has thousands of logic blocks and hard embedded micros spread across the FPGA chip, more numbers of routing lines and switch boxes are required. Also the clock network is built with same routing resources. The Configurable logic blocks with clock gating will allow reducing the dynamic power. The logical equivalence of CLB inputs will help to reduce the routing congestion and also improve the timing of the design.
Keywords: FPGA, VTR, clock gating, CLB, ODIN II
Edition: Volume 4 Issue 6, June 2015,
Pages: 23 - 26
How to Cite this Article?
Abhijeet Khandale, Dr. H R Bhagyalakshmi, "Low Power FPGA Architecture", International Journal of Science and Research (IJSR), Volume 4 Issue 6, June 2015, pp. 23-26, https://www.ijsr.net/get_abstract.php?paper_id=SUB153748
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