International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




Downloads: 106

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 4, April 2015


RTL Design and FPGA Implementation of Canny Edge Detector with Real Time Threshold Adjustment Capability

Lakshmamma K M | Chandana B.R


Abstract: The Canny edge detector is an edge detection operator detect a wide range of edges in images. Canny edge detector is read both column and rows pixels in images this is extra feature we are added in our article. Canny Edge detector is very fast and easy detector compared other detector like sobel detector. Edge detection is a very important area in the field of Computer Vision. Edges define the boundaries between regions in an image, which helps with segmentation and object recognition. Compared with the implementation in a PC based system, pipelined implementation on FPGA is easy way and it takes much less implementation time and also more efficiency. Then also we are improving Thresholding.


Keywords: NMAX, RTL, FPGA, PC, DSP


Edition: Volume 4 Issue 4, April 2015,


Pages: 1730 - 1732


How to Cite this Article?

Lakshmamma K M, Chandana B.R, "RTL Design and FPGA Implementation of Canny Edge Detector with Real Time Threshold Adjustment Capability", International Journal of Science and Research (IJSR), Volume 4 Issue 4, April 2015, pp. 1730-1732, https://www.ijsr.net/get_abstract.php?paper_id=SUB153402

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