International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064


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Research Paper | Computer Science & Engineering | India | Volume 4 Issue 4, April 2015


Preparation of Test Data from the Simulated and Test Beam Data for Testing the ATLAS New Small Wheel FPGA-Based Trigger Processor

Jayasree S, Reshmy V R, Dr. Lorne Levinson


Abstract: This paper deals with the development of a test program for testing the FPGA based trigger processor for the ATLAS detector in LHC experiment in CERN. This detector will be upgraded in order to benefit more from the high luminosity. As the luminosity increases there will be large number of fake data will be produced. To filter this fake trigger a three level trigger system is used. The trigger processor is a hardware (FPGA) processor that receives data from the ATLAS detector. In order to develop and test the trigger algorithm we need to inject simulated data into the processors input path. The ATLAS detector simulation programs generate hits in detectors. We also have real detector data recorded in test beams. Both must be processed to provide the input expected by the trigger processor.


Keywords: CERN, ATLAS, LHC, Higgs Bosons, Muons


Edition: Volume 4 Issue 4, April 2015,


Pages: 681 - 684


How to Cite this Article?

Jayasree S, Reshmy V R, Dr. Lorne Levinson, "Preparation of Test Data from the Simulated and Test Beam Data for Testing the ATLAS New Small Wheel FPGA-Based Trigger Processor", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SUB153205, Volume 4 Issue 4, April 2015, 681 - 684

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