Design and Implementation of High-performance Logic Arithmetic Full Adder Circuit based on FinFET 16nm Technology - Shorted Gate Mode
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 4, April 2015

Design and Implementation of High-performance Logic Arithmetic Full Adder Circuit based on FinFET 16nm Technology - Shorted Gate Mode

Priyanka P, Vasundhara Patel K S

Fin-type eld-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. FinFETs are double-gate and multi-gate devices. Double-gate (DG) FinFETs has better Short Channels Effects (SCEs) performance compared to the conventional CMOS and stimulates technology scaling. The two gates of a FinFET can either be shorted for higher performance or independently controlled for lower leakage or reduced transistor count. In this paper, we are designing a 16nm Double-gate (DG) FinFETs and extracting their transfer characteristics by using Synopsys HSPICE simulation tool. Full Adder is implemented in CMOS with 32nm technology and FinFET-shorted gate mode with 16nm technology along with its working waveform and performance analysis. HSPICE simulations are carried out for the design and results are analyzed.

Keywords: Double-gate FinFET DGFinFET, Multi-gate MG, Short channel effects SCE, Shorted-Gate Mode SG-Mode, Drain Induced Barrier Lowering DIBL, Full Adder

Edition: Volume 4 Issue 4, April 2015

Pages: 490 - 494

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How to Cite this Article?

Priyanka P, Vasundhara Patel K S, "Design and Implementation of High-performance Logic Arithmetic Full Adder Circuit based on FinFET 16nm Technology - Shorted Gate Mode", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB152908, Volume 4 Issue 4, April 2015, 490 - 494

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