Analysis of Implicit Type Pulse Triggered Flip Flop
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 3, March 2015

Analysis of Implicit Type Pulse Triggered Flip Flop

Richa Srivastav, Dinesh Chandra, Sumit Khandelwal

In this paper, analysis of the pulse triggered flip flop is done. We compare the several styles of implicit type pulse triggered flip flop. In order to reduce the power consumption, conditional enhancement technique is used which speed-up the discharge path along the critical path. This was confirmed by simulation using 90nm technology, 1.0V power supply and clock frequency of 500MHz

Keywords: Low Power, Pulse Triggered, flip flop

Edition: Volume 4 Issue 3, March 2015

Pages: 2158 - 2160

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How to Cite this Article?

Richa Srivastav, Dinesh Chandra, Sumit Khandelwal, "Analysis of Implicit Type Pulse Triggered Flip Flop", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB152635, Volume 4 Issue 3, March 2015, 2158 - 2160

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