Review on Floating Point Multiplier Using Vedic Mathematics
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Review Papers | Engineering Science | India | Volume 4 Issue 2, February 2015

Review on Floating Point Multiplier Using Vedic Mathematics

Sneha Khobragade, Mayur Dhait

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using ancient Vedic mathematics is presented. The idea for designing the multiplier unit is adopted from ancient Indian mathematics Vedas. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise, vertically means straight above multiplication and crosswise means diagonal multiplication and taking their sum. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. On account of these formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB.

Keywords: Urdhva-Tiryakbhyam sutra, VHDL

Edition: Volume 4 Issue 2, February 2015

Pages: 1499 - 1502

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How to Cite this Article?

Sneha Khobragade, Mayur Dhait, "Review on Floating Point Multiplier Using Vedic Mathematics", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB151555, Volume 4 Issue 2, February 2015, 1499 - 1502

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