Functional Broadside Test Generation for Fault Analysis
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Case Studies | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015

Functional Broadside Test Generation for Fault Analysis

Greeshma U. R., Sarath Raj S.

When the clock frequency of the integrated circuits increases, timing related defects may occur and it is necessary to find them. The timing defects are modeled by delay faults. Transition faults are used as the delay fault model. The effect of a transition fault at a point in a circuit is that, the transition that occur at that point will not reach the flip flop or a primary output within the desired clock period of the circuit. Existing methods for testing includes Enhanced scan, Skewed load and Broadside tests. They may cause over testing. The Functional broadside test, which is a two pattern test, avoids this over testing by using only reachable states. It is a broadside test that creates in its functional clock cycles, the same state transitions that may occur during functional operation. Earlier procedures generate test sets offline for application from an external tester. Here, the circuit is used to obtain reachable states during test. Pairs of consecutive time units of the primary input sequences can be used to produce two pattern tests. They are called functional, since they use reachable states which are also possible during the functional operation.

Keywords: Functional broadside tests, LFSR, Reachable states, Transition fault, Two pattern test

Edition: Volume 4 Issue 2, February 2015

Pages: 1673 - 1676

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Greeshma U. R., Sarath Raj S., "Functional Broadside Test Generation for Fault Analysis", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB151546, Volume 4 Issue 2, February 2015, 1673 - 1676

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