International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064


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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 1, January 2015


An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating

Bhima Venkata Sujatha, V. T. Venkateswarlu


Abstract: In this paper, a new method for minimizing power dissipation in 4-bit Johnson up-down counter is proposed. In this design, we have used a dual dynamic pulsed flip-flop (DDFF) [1], which supports embedding a logic module (DDFF-ELM) and a power saving technique, namely, clock gating [2] is used. We have used DDFF because it is power efficient compared to other flip-flops in the literature. We have used digital schematic editor (DSCH) for designing, simulation and layout generation is done using Microwind. From the simulation results, it is observed that power dissipation is reduced by 33.9 %.


Keywords: Johnson counter, DDFF-ELM, DSCH, Microwind, clock gating


Edition: Volume 4 Issue 1, January 2015,


Pages: 2723 - 2728


How to Cite this Article?

Bhima Venkata Sujatha, V. T. Venkateswarlu, "An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SUB151000, Volume 4 Issue 1, January 2015, 2723 - 2728

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