A CMOS Current-Mode Full-Adder Cell for Multi Valued Logic VLSI
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 12, December 2014

A CMOS Current-Mode Full-Adder Cell for Multi Valued Logic VLSI

Ravi Ranjan Kumar, Priyanka Gautam

The thesis describes the design and implementation of a carry save adder cell for multivalued logic VLSI. A four-valued system was chosen and the logic was analyzed and minimized using the C HAMLET CAD tool [I]. SPICE was used to design and simulate the required behaviour of the current-mode CMOS circuits. A VLSI test and evaluation integrated circuit was implemented with MAGIC and fabricated through the MOSIS service. The completed IC was tested and evaluated using a specially designed binary-to multi- valued logic converter and decoder. Engineering modifications to the original current-mode inverter cells used by HAMLET were made leading to significant power savings in a complete design. The fabricated device performed as predicted by SPICE simulation. Exhaustive functional testing produced correct steady-state output signals for all cases of input loadings. Finally, we show HAMLET minimization heuristics are not efficient in the design of adder cells by comparison with an alternative modulo 4 carry save adder cell in current-mode CMOS.

Keywords: CMOS, CAD, SPICE, HAMLET

Edition: Volume 3 Issue 12, December 2014

Pages: 426 - 431

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Ravi Ranjan Kumar, Priyanka Gautam, "A CMOS Current-Mode Full-Adder Cell for Multi Valued Logic VLSI", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB14334, Volume 3 Issue 12, December 2014, 426 - 431

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