International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 12, December 2014

Design of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique

Juliet Abraham, Dr. B. Paulchamy

CMOS is used to construct the integrated circuits with low level of static leakage. With this low level leakage we are designing all the transistor circuits in CMOS logic. To control this static leakage in the circuits the supply voltage is a major concern. Here the step-up converters with charge pump and the level for maintaining its threshold voltage (VT) is to be analyzed and proposed. Here we are going to propose the novel approach as body bias effect and sub-threshold logic. This will be applied for the step-up converters for energy harvesting applications. The backward control is to be processed for control the internal voltage when the charge transfer switch could be in activation. When the supply voltage is to be raise from the fixed voltage level it will be turn OFF the transistor. The maximum level of the converters circuits contain the branch A and branch B which could be contains all p-MOS and n-MOS combinations. The oscillator circuit also to e designed and applied to the proposed six stage charge pump circuit to reduce the power consumption. To reduce the standby mode leakage we are designing the circuit by using power gating logic. These circuits are to be designed and verified by using the TANNER T-SPICE TOOLS.

Keywords: Low power, Charge pump, Body bias, CMOS logic

Edition: Volume 3 Issue 12, December 2014

Pages: 411 - 415


How to Cite this Article?

Juliet Abraham, Dr. B. Paulchamy, "Design of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB14307, Volume 3 Issue 12, December 2014, 411 - 415

20 PDF Views | 10 PDF Downloads

Download Article PDF

Video Lecture of Above Article is Not Available Yet

You be the First to Request! Press the Button below!



Similar Articles with Keyword 'Low power'

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1779 - 1783

Low Power Variable Latency Multiplier With AH Logic

Roobitha Nujum, Jini Cheriyan

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1441 - 1445

Design of Low Power Phase Frequency Detectors and VCO using 45nm CMOS Technology

Rajani Kanta Sutar, M.Jasmin, S. Beulah Hemalatha

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1262 - 1265

Design of CMOS Tapered Buffer for High Speed and Low Power Applications using 65nm Technology

Ankur Saxena, Payal Kaushik

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2218 - 2222

A Power Efficient Design of Reversible RAM Using Pseudo Reed-Muller Expression

Shibinu A. R, Rajkumar.P

Share this article

Research Proposals or Synopsis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2277 - 2280

An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits

Avinash Singh, Dr. Subodh Wairya

Share this article

Similar Articles with Keyword 'Charge pump'

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1338 - 1340

A Review of Phase Lock Loop Techniques used in Communication Engineering

Piyush Kumar Singh, Bhagwat Kakde

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 7 Issue 5, May 2018

Pages: 727 - 732

Design and Implementation of a PLL using a Single-Event-Transient Hardened-by-Design (SETHBD) Charge Pump

Pallavi. K. R, Dr. K. N. Muralidhara

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 12, December 2014

Pages: 411 - 415

Design of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique

Juliet Abraham, Dr. B. Paulchamy

Share this article

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 26 - 31

Online Case Study On Phase Frequency Detector

Ashwini Rajole

Share this article

Similar Articles with Keyword 'Body bias'

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 842 - 844

A Review and Comparative Study of Different Low Power Consumption Techniques

Amit Saraswat, Ekta Jolly

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 12, December 2014

Pages: 411 - 415

Design of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique

Juliet Abraham, Dr. B. Paulchamy

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 845 - 851

Design of Low Power Voltage Controlled Ring Oscillator Using MTCMOS Technique

Neeta Yadav, Sakshi Gupta

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 847 - 850

Speed Analysis of Body Biased TSPC and ETSCPC Flip Flops

Nemitha B, Pradeep Kumar B. P

Share this article

Similar Articles with Keyword 'CMOS logic'

Research Proposals or Synopsis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2277 - 2280

An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits

Avinash Singh, Dr. Subodh Wairya

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 1597 - 1602

Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power

Vema Vishnu Priya, G.Ramesh

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1205 - 1210

A Novel Low power and Area Efficient Carry-Lookahead Adder Using MOD-GDI Technique

Pinninti Kishore, P. V. Sridevi, K. Babulu, K.S Pradeep Chandra

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 1297 - 1300

A Wide Range Level Shifter Using a Self Biased Cascode Current Mirror

Tejas S. Joshi, Priya M. Nerkar

Share this article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1214 - 1218

Review on Different Types of Power Efficient Adiabatic Logics

Vijendra Pratap Singh, Dr. S.R.P Sinha

Share this article

Top