VLSI Implementation of Discrete Wavelet Transform Using Systolic Array Architecture for Daubechies3 Wavelet
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 12, December 2014

VLSI Implementation of Discrete Wavelet Transform Using Systolic Array Architecture for Daubechies3 Wavelet

Rashmi Patil, Dr. M. T. Kolte

The wavelet transform has itself a useful tool in the field of 1-dimensional and 2-dimensional signal compression systems. Due to the growing importance of this technique, there is an increasing need in many working groups for having a development environment which could be flexible enough and where the performance of a specific architecture could be measured, closer to reality rather than in a theoretical way. Our work is new, simple and efficient VLSI architecture for computing the Discrete Wavelet Transform (DWT).The proposed architecture is systolic in nature, modular and extendible to 1-D DWT transform of any size. The systolic array architecture (DWT-SA) has been designed, simulated and implemented in VLSI. Being systolic in nature, the architecture can compute DWT at a rate of N106 samples/sec corresponding to a clock speed of N MHzs.

Keywords: DWT, FRA, hardware efficiency, six tap Fir Filter, Systolic Array

Edition: Volume 3 Issue 12, December 2014

Pages: 2342 - 2351

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Rashmi Patil, Dr. M. T. Kolte, "VLSI Implementation of Discrete Wavelet Transform Using Systolic Array Architecture for Daubechies3 Wavelet", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB141030, Volume 3 Issue 12, December 2014, 2342 - 2351

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