International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




Downloads: 1 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Review Papers | Electronics & Communication Engineering | India | Volume 11 Issue 4, April 2022


Review for Design Considerations of SAR ADC in CMOS 32 NM Technology

Monu Thool | Dr. Girish D. Korde | Prof. Anant W. Hinganikar


Abstract: Analog-to-Digital Converters (ADCs) are key components for the design of power limited systems, in order to keep the power consumption as low as possible. Among all ADCs, Successive Approximation Register (SAR) ADCs are mostly used due to their simpler structure, fewer analog blocks, smaller area, and lower power consumption. This review paper is focuses on a study to summarize developments in SAR based ADC. It also focuses on the new CMOS 32nm technology and on some major designing components, parameters like area, power, current and techniques analysis like parametric, delays, speed critical paths and cross talks while designing a SAR ADC.


Keywords: ADC, SAR, CMOS 32nm Technology, Low power, comparator, sample-and-hold


Edition: Volume 11 Issue 4, April 2022,


Pages: 516 - 519

Review for Design Considerations of SAR ADC in CMOS 32 NM Technology


How to Cite this Article?

Monu Thool, Dr. Girish D. Korde, Prof. Anant W. Hinganikar, "Review for Design Considerations of SAR ADC in CMOS 32 NM Technology", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SR22405181953, Volume 11 Issue 4, April 2022, 516 - 519, #ijsrnet

How to Share this Article?

Enter Your Email Address




Similar Articles with Keyword 'ADC'

Downloads: 97

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 1672 - 1675

The Design of Multi Bit Quantizer Sigma-Delta Modulator Analog to Digital Converter

J. Snehalatha

Share this Article

Downloads: 100

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2835 - 2838

Efficient Implementation of Digital Receiver on FPGA

M. Sravani | B. Madhavi

Share this Article


Top