VLSI Architecture Design and Implementation of CANNY Edge Detection Subsystem
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 10 Issue 3, March 2021

VLSI Architecture Design and Implementation of CANNY Edge Detection Subsystem

Ragi R G, Jayaraj U Kidav, Roshith K

In Edge detection is one of the most fundamental algorithms in digital image processing. The Canny edge detector is the most implemented edge detection algorithm because of its ability to detect edges even in images that are intensely contaminated by noise. In this paper, a modified canny edge detector is designed implemented in MATLAB and implemented in FPGA. The mask for gradient calculation and in non-maximal suppression bilinear interpolation of four pixels are considered. This edge detector is implemented as a preprocessing stage in iris detection subsystem. The motivation in designing the hardware modules of canny edge detector was to reduce its complexity, enhance its performance and to make it suitable development on a reconfigurable FPGA based platform for VLSI implementation.

Keywords: Edge Detection, Canny Edge detector, FPGA

Edition: Volume 10 Issue 3, March 2021

Pages: 143 - 150

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How to Cite this Article?

Ragi R G, Jayaraj U Kidav, Roshith K, "VLSI Architecture Design and Implementation of CANNY Edge Detection Subsystem", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SR21301101835, Volume 10 Issue 3, March 2021, 143 - 150

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