International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064


Downloads: 63

Research Paper | Electronics & Telecommunication Engineering | India | Volume 10 Issue 2, February 2021


CNTFET Based Ternary Multiplier Circuit

Pradeep Singh Yadav, Anurag Nair


Abstract: This paper presents the design of 2-bit ternary multiplier circuit using CNTFET. Ternary logic is a multi-valued logic (MVL) which is a better substitute for traditional binary logic (Two level Logic) as MVL reduces the chip complexity by reducing the number if interconnections and this in turn reduces the chip area required to implement the circuitry. Power consumption and power delay product is also reduced with the use of MVL. CNTFET’s are used to design the ternary logic circuits. CNTFET’s threshold voltages can be varied by varying the diameters of nanotubes. In this paper 2-bit ternary multiplier circuit using CNTFET is designed using 32nm technology.


Keywords: Binary Multiplexer, Ternary Multiplexer, CMOS, CNTFET, MVL, MOSFET, Ternary Logic, Ternary Decoder


Edition: Volume 10 Issue 2, February 2021,


Pages: 543 - 547


How to Cite this Article?

Pradeep Singh Yadav, Anurag Nair, "CNTFET Based Ternary Multiplier Circuit", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SR21208154250, Volume 10 Issue 2, February 2021, 543 - 547

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