International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




Downloads: 101

Research Paper | Computer Engineering | Iraq | Volume 9 Issue 6, June 2020


FPGA based MIPS Pipeline Processor with SIMD Architecture

Sarah M. Al-Sudany | Ahmed S. Al-Araji [2] | Bassam M. Saeed


Abstract: The aim of this study is to develop a MIPS pipeline processor based on FPGA with using VHDL. This architecture can be used for academic purposes and to set up a multifunctional system for the processing of digital signals or images. In order to do so, a subset of MIPS instructions is chosen to show functionality in the simulation and synthesis processor inside a five-stage pipeline (instruction fetch, instruction decode, execution, memory and writing back). The hazard control network has been set up to manage data transfer and stalling. A single cycle multiplication functionality and a single-cycle SIMD instruction have been added to the basic MIPS architecture. The SIMD instructions have been selected to execute binary operations for possible mathematical morphology. A Software (XUP) box containing Xilinx Virtex7 xc7vx330t FPGA was the board used to test the processor. This makes it possible for the processor to perform four 32-bit data sets per cycle when the SIMD pipeline is complete. The research explained the Field Programmable Gate Array (FPGA) technology with extensive explore of MIPS pipeline architecture. In addition to the research highlights many aspect of this process such as the role of The SIMD principle in the support of the hardware acceleration feature that required by multicore overall processors and instruction set and the multiple instructions executed in this processor from each register and multiply them as standard MIPS applications instead of the entire 32 bits.


Keywords: MIPS Pipeline Processor, SIMD Architecture, FPGA, RTL, VHDL


Edition: Volume 9 Issue 6, June 2020,


Pages: 444 - 450


How to Cite this Article?

Sarah M. Al-Sudany, Ahmed S. Al-Araji, Bassam M. Saeed, "FPGA based MIPS Pipeline Processor with SIMD Architecture", International Journal of Science and Research (IJSR), Volume 9 Issue 6, June 2020, pp. 444-450, https://www.ijsr.net/get_abstract.php?paper_id=SR20601000556

How to Share this Article?

Enter Your Email Address




Similar Articles with Keyword 'Architecture'

Downloads: 110 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper, Computer Engineering, India, Volume 9 Issue 2, February 2020

Pages: 1513 - 1518

Consensus Mechanisms in Blockchain Technology: A Review

Sankaliya Shraddha

Share this Article

Downloads: 207

Research Paper, Computer Engineering, Iraq, Volume 9 Issue 3, March 2020

Pages: 529 - 532

Implementation of Run Length Encoding Using Verilog HDL

Hayder Waleed Shnain | Mohammed Najm Abdullah [6] | Hassan Awheed Jeiad [3]

Share this Article


Top