Implementation and Comparison of Tree Multiplier using Different Circuit Techniques
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Downloads: 106 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 9, September 2014

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Multiplication is an important fundamental function in arithmetic operations and is used in various applications. Tree multiplier is a high speed parallel multiplier used for large size operands. In this paper 4x4 Tree multiplier is implemented with CMOS logic, CPL logic and DPL logic technique and various performance parameters such as power, delay and transistor count of Tree Multiplier using different circuit techniques are discussed and compared. Different types of circuit techniques have a unique pattern of structure to improve their performance in various means like low power, minimal delay and decreased PDP. All the circuits are designed and simulated using 90nm technology, 2.5V supply Also layouts of all the basic circuits (AND2 and Full Adder) using CMOS logic, CPL logic and DPL logic are designed and the layout of the Tree multiplier using CMOS logic is designed and verified by its corresponding waveform.

Keywords: Full adder, AND gate, Tree Multiplier, 3: 2 compressor, CMOS, CPL, DPL

Edition: Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Share this Article

How to Cite this Article?

Subhag Yadav, Vipul Bhatnagar, "Implementation and Comparison of Tree Multiplier using Different Circuit Techniques", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SEP14611, Volume 3 Issue 9, September 2014, 2276 - 2280

Enter Your Registered Email Address





Similar Articles with Keyword 'Full adder'

Downloads: 105 | Weekly Hits: ⮙1 | Monthly Hits: ⮙10

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 943 - 949

Design and Analysis of CMOS Multipliers at 180nm and 350nm

Jagmeet Singh, Hardeep Singh

Share this Article

Downloads: 106 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Share this Article

Downloads: 107 | Weekly Hits: ⮙2 | Monthly Hits: ⮙10

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2827 - 2831

Analysis of Modified Hybrid Full Adder with High Speed

Jigyasa, Kumar Saurabh

Share this Article

Downloads: 108 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Comparative Studies, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 764 - 767

Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology

Umashankar Dhepra, Rajkumar Gehlot

Share this Article

Downloads: 108 | Weekly Hits: ⮙3 | Monthly Hits: ⮙8

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015

Pages: 2383 - 2388

Design and Analysis of Dynamic Current Mode Full Adder with reduced Power and Delay

Dr. S.R.P. Sinha, Namita Tiwari

Share this Article

Similar Articles with Keyword 'AND gate'

Downloads: 103 | Weekly Hits: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 10, October 2014

Pages: 2221 - 2224

Implementation of Low Power Ternary Logic Gates using CMOS Technology

V. T. Gaikwad, Dr. P. R. Deshmukh

Share this Article

Downloads: 105 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 3321 - 3325

Comparative Study on Logic Gates Using Bulk Transmission Gate and Double Gate Transmission Gate

Sima Baidya, Arindam Chakraborty

Share this Article

Downloads: 106 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Share this Article

Downloads: 106 | Monthly Hits: ⮙11

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 2270 - 2274

Design and Simulation of NOT and NAND Gate Using Hybrid SET-MOS Technology

Daya Nand Gupta, S. R. P. Sinha

Share this Article

Downloads: 113 | Monthly Hits: ⮙8

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 4, April 2013

Pages: 183 - 187

A Novel Pass Transistor Logic Based Pulse Triggered Flip-flop with Conditional Enhancement

Shakthipriya.R, Kirthika.N

Share this Article

Similar Articles with Keyword 'Tree Multiplier'

Downloads: 105 | Weekly Hits: ⮙1 | Monthly Hits: ⮙10

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 943 - 949

Design and Analysis of CMOS Multipliers at 180nm and 350nm

Jagmeet Singh, Hardeep Singh

Share this Article

Downloads: 106 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Share this Article

Downloads: 111 | Weekly Hits: ⮙2 | Monthly Hits: ⮙12

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 1069 - 1074

Design for Low Power Multiplier Based On Fixed Width Replica Redundancy Block & Compressor Trees

Mariya Stephen, Vrinda

Share this Article

Downloads: 113 | Monthly Hits: ⮙14

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 741 - 743

Digital Multipliers: A Review

Jyoti Sharma, Sachin Kumar

Share this Article

Downloads: 124 | Weekly Hits: ⮙4 | Monthly Hits: ⮙9

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2387 - 2390

Design of Wallace Tree Multiplier using Adiabatic Logic

Bhushan V. Mude, Prof. R. N. Mandavgane, Prof. A. P. Bagde

Share this Article

Similar Articles with Keyword 'CMOS'

Downloads: 93 | Weekly Hits: ⮙2 | Monthly Hits: ⮙14

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014

Pages: 481 - 483

Communication of Multi Mobile-Robots Based On ZigBee Network

Taskeen Sultana, Zeenath

Share this Article

Downloads: 99 | Weekly Hits: ⮙1 | Monthly Hits: ⮙8

Research Paper, Electronics & Communication Engineering, Sudan, Volume 3 Issue 7, July 2014

Pages: 1756 - 1759

Verification of a Readout Design for Multiple Energy Discrimination working in Single Photon Processing Pixel Array

Suliman Abdalla, Bengt Oelmman, Amin Babiker

Share this Article

Downloads: 101 | Monthly Hits: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 1597 - 1602

Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power

Vema Vishnu Priya, G.Ramesh

Share this Article

Downloads: 103 | Weekly Hits: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 10, October 2014

Pages: 2221 - 2224

Implementation of Low Power Ternary Logic Gates using CMOS Technology

V. T. Gaikwad, Dr. P. R. Deshmukh

Share this Article

Downloads: 104 | Weekly Hits: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2433 - 2438

A Novel Design of Low Power 4:2 Compressor using Adiabatic Logic

Shaswat Singh Bhardwaj, Vishal Moyal

Share this Article

Similar Articles with Keyword 'CPL'

Downloads: 105 | Weekly Hits: ⮙1 | Monthly Hits: ⮙10

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 943 - 949

Design and Analysis of CMOS Multipliers at 180nm and 350nm

Jagmeet Singh, Hardeep Singh

Share this Article

Downloads: 106 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Share this Article

Downloads: 106 | Monthly Hits: ⮙7

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 2177 - 2182

Development of Wireless RGB LED PWM Controller on Low Cost CPLD

Kamal Kant Sharma, Vipin Kumar Gupta

Share this Article

Downloads: 106 | Weekly Hits: ⮙6 | Monthly Hits: ⮙12

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1489 - 1492

Review on Design of PWM Controller Using FPGA

Sneha Kirnapure, Vijay R. Wadhankar

Share this Article

Downloads: 114 | Weekly Hits: ⮙2 | Monthly Hits: ⮙12

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1194 - 1199

VLSI based Fuzzy Logic Static Voltage Regulation System

Vibha Sharma, Vipin Kumar Gupta

Share this Article

Similar Articles with Keyword 'DPL'

Downloads: 105 | Weekly Hits: ⮙1 | Monthly Hits: ⮙10

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 943 - 949

Design and Analysis of CMOS Multipliers at 180nm and 350nm

Jagmeet Singh, Hardeep Singh

Share this Article

Downloads: 106 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Share this Article

Downloads: 119 | Weekly Hits: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 4, April 2017

Pages: 1915 - 1919

Low-Power and High?Performance Design Techniques for CMOS 4-bit ALU by using CPL, DPL, DVL

Jagruty Naik

Share this Article



Top