High Speed Advanced Encryption Standard Using Pipelining
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014

High Speed Advanced Encryption Standard Using Pipelining

Mradul Upadhyay, Utsav Malviya

In this paper we have proposed high throughput by swapping the AES algorithm internal stages in this proposed work shift row is operated before sub bytes (substitution bytes). In this proposed operation the AES encryption operation will not effect, with this process is streamlines the processes a 4 block of data rather then 16 block. The advantage of this is we can save area. This process repeats for 10 cycles and with the help of this we can encrypt 128 bits data with higher throughput. We have evaluated this performance of higher throughput and hardware area in Xilinxs 12.2 vertex 4 XC4VFX140-11FF1517.

Keywords: Advanced Encryption Standard AES, Register Transfer Logic RTL, Very High Speed Integrated Circuit Hardware Description Language VHDL, Galois field GF, Byte Substitution Sub Byte

Edition: Volume 3 Issue 11, November 2014

Pages: 779 - 782

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How to Cite this Article?

Mradul Upadhyay, Utsav Malviya, "High Speed Advanced Encryption Standard Using Pipelining", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT14915, Volume 3 Issue 11, November 2014, 779 - 782

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