A Review on Reversible Logic Gate Multipliers
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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Review Papers | Electronics & Communication Engineering | India | Volume 3 Issue 10, October 2014

A Review on Reversible Logic Gate Multipliers

Supreetha Rao, Supreetha M, Vidya Venkatesh, Prajna

The efficient low power and small area multipliers in the digital circuits for the emerging technology are of more interest these days. Hence designing of the multipliers with the factors of low power, area and delay is dominant. For this purpose the reversible logic multipliers are designed in advantage over that of conventional multipliers. This paper describes the comparative analysis of different reversible logic gate multipliers in terms of number gates, number of garbage inputs, garbage outputs and quantum cost. Each of the multipliers operation can be generalized for NxN bit multiplication of their advantages.

Keywords: multipliers, reversible logic, garbage output, garbage input, quantum cost

Edition: Volume 3 Issue 10, October 2014

Pages: 2286 - 2288

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How to Cite this Article?

Supreetha Rao, Supreetha M, Vidya Venkatesh, Prajna, "A Review on Reversible Logic Gate Multipliers", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT14757, Volume 3 Issue 10, October 2014, 2286 - 2288

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