Implementation of Low Power Ternary Logic Gates using CMOS Technology
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 10, October 2014

Implementation of Low Power Ternary Logic Gates using CMOS Technology

V. T. Gaikwad, Dr. P. R. Deshmukh

This paper describes the architecture, design & simulation of ternary logic gates. In a VLSI circuit, approximately 70 percent of the area is devoted to interconnection, 20 percent to insulation, and 10 percent to devices. The binary logic is limited due to interconnect which occupies large area on a VLSI chip. In this work, the designs of ternary-valued logic circuits have been explored over multi-valued logic. The proposed GATES are designed & simulated with the help of Microwind EDA tool. s. These Gates are implemented using C-MOS ternary logic (T-Gates) The new family is based on CMOS technology and is thus open to VLSI implementation. The proposed design is comprised of a set of inverters, NOR gates, and NAND gates. The designed technique used here requires the width and length calculations of the CMOS gates to improve thef the design. The proposed logic can be implemented at its layout side using 45 nm technologies.

Keywords: Ternary, Multi valued logic, CMOS, VLSI

Edition: Volume 3 Issue 10, October 2014

Pages: 2221 - 2224

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How to Cite this Article?

V. T. Gaikwad, Dr. P. R. Deshmukh, "Implementation of Low Power Ternary Logic Gates using CMOS Technology", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT14633, Volume 3 Issue 10, October 2014, 2221 - 2224

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