International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Double Blind Reviewed

ISSN: 2319-7064


Downloads: 109

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014


FPGA Implementation of Motion Feature Extraction Employing Pipelined Architecture

M. Nivethitha | B. Venkataramanaiah


Abstract: A VLSI is capable of extracting motion features from moving images in real time has been developed by employing parallel architecture. Image processing is a method to convert an image into form and perform some operations in order to get an enhanced image to extract useful information from it. It is a type of signal dispensation in which input is image like video frame or photograph and output maybe image or characteristics associated with that image. Image processing includes treating images as two dimensional signals while applying already set of processing methods to them. Image segmentation is the division of image; The simplest method is thresholding technique. The proposed method is to achieve real time response of the system a pixel parallel architecture has been explored in binarization of filtered images of feature extraction. A Background subtraction method is a general method of motion detection. It is a technology that uses the differences of current image and background image to detect moving object. And we implement in FPGA by employing a pipelined architecture.


Keywords: feature extraction, video surveillance, motion detection, background subtraction


Edition: Volume 3 Issue 11, November 2014,


Pages: 2202 - 2204


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How to Cite this Article?

M. Nivethitha, B. Venkataramanaiah, "FPGA Implementation of Motion Feature Extraction Employing Pipelined Architecture", International Journal of Science and Research (IJSR), Volume 3 Issue 11, November 2014, pp. 2202-2204, https://www.ijsr.net/get_abstract.php?paper_id=OCT141395

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