Low Power Spectral Analysis for Built in Self Test by Using System on Chip
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014

Low Power Spectral Analysis for Built in Self Test by Using System on Chip

L. Maheswari, B. V. P. Prasad

The Fast Fourier Transform Algorithm is used for Time to Frequency transform in the receiver side for spectral analysis in the communication. In the 4th Generation, the presence of multiple tones requires fine frequency tuning, which imposes the use of a large number of FFT points. FFT analysis is based on the coherent sampling, but it requires a significantly smaller number of points to make the FFT realization more suitable for on-chip built-in testing and calibration applications that require area and power efficiency. Due to large number of FFT points, more butterfly units are required that leads to large numbers of spectrum with testing complexity. Since all the processing elements are inside a single chip, there is a possible to get distortion. To get the accurate signal, we are using March C- algorithm with reconfigurable Pulse Width Controller is proposed makes way to reduce FFT points with address repetition aware process. Thus the accuracy has been maintained.

Keywords: Fast Fourier Transform FFT, coherent sampling, ADC, spectral testing

Edition: Volume 3 Issue 11, November 2014

Pages: 1723 - 1726

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How to Cite this Article?

L. Maheswari, B. V. P. Prasad, "Low Power Spectral Analysis for Built in Self Test by Using System on Chip", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT141289, Volume 3 Issue 11, November 2014, 1723 - 1726

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