Nano Technology
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014

Nano Technology

Sagar P. More, M. A. Khan

we present a new approach using genetic algorithms, neural networks, and nano robotics concepts applied to the problem of control design for nanoassembly automation and its application in medicine. As a practical approach to validate the proposed design, we have elaborated and simulated a virtual Environment focused on control automation for nano robotics teams that exhibit collective behavior. This collective behavior is a suitable way to perform a large range of tasks and positional assembly manipulation in a complex three-dimensional workspace. We emphasize the application of such techniques as a feasible approach for the investigation of nano robotics system design in nano medicine. Theoretical and practical analyses of control modeling is one important aspect that will enable rapid development in the emerging field of nanotechnology.

Keywords: Assembly nanao manipulation, nono medicine, proposed Design, nanotechnology

Edition: Volume 3 Issue 11, November 2014

Pages: 1339 - 1345

Share this Article

How to Cite this Article?

Sagar P. More, M. A. Khan, "Nano Technology ", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT141246, Volume 3 Issue 11, November 2014, 1339 - 1345

91 PDF Views | 76 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'proposed Design'

Research Paper, Electronics & Communication Engineering, Egypt, Volume 5 Issue 4, April 2016

Pages: 2089 - 2093

Design of Switched Resistor ?? ADC Using VHDL-AMS Tool

Ahmed Osman Hamaad, Mohyldin A. Abo-Elsoud, A. M. Abo-Talib

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3033 - 3036

FIR Interpolation Filter for Multi-Standard Digital Up Converter Using FPGA

Chaithra M. R., Yashwanth N

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 1272 - 1276

Low Power, Low Voltage 95.1-dB Linear Variable Gain Amplifier with Diode Connected Load

Pashupati Nath Jha, Vinod Kapse

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 909 - 913

Implementation of 100BASE-T4 Network Repeater Using FPGA

Sudarshan M. Dighade, Pranav P. Kulkarni

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 6 Issue 11, November 2017

Pages: 2142 - 2145

Novel Design of Low Power Nonvolatile 10T1R SRAM Cell

Vani Tripathi, Bhawna Trivedi

Share this Article

Similar Articles with Keyword 'nanotechnology'

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 2143 - 2148

Design and Implementation of 8 BIT Vedic Multipliers USING HNG Gates

Illa Bharti, Manisha Waje

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1475 - 1478

New Design for Obtain Fault Tolerant Logic Gate Using Quantum-Dot Cellular Automata

Punam Prabhakar Bhalerao, Sameena Zafar

Share this Article

Survey Paper, Electronics & Communication Engineering, India, Volume 7 Issue 4, April 2018

Pages: 1426 - 1428

A View at Nanophotonics

Reena Kulkarni, Priyadarshini K Desai, Keerti Kulkarni

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 901 - 904

Low Power 8 Bit quantum ALU Implementation Using Reversible Logic Structure

Vijay G. Roy, P. R. Indurkar, D. M. Khatri

Share this Article

Review Papers, Electronics & Communication Engineering, India, Volume 5 Issue 1, January 2016

Pages: 474 - 479

A Study of Single Electron Transistor (SET)

Monika Gupta

Share this Article
Top