M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 10, October 2014
6-Bit Flash ADC for High speed Applications
N. Bharat Kumar Reddy, Sri D. Sharath Babu Rao
This paper shows the implementation of a 6-bit Flash Analog to Digital Converter in 130-nm technology CMOS logic functions at 2.5-GSamples/s, used in most of DSP-based receiver. The FLSH ADC is equipped by variable gain amplifier (VGA), track-and-hold (T/H) circuit, a comparator array consist of 63 comparators, D Flip-Flops. A multiplexer logic is compared with the decoder using Full Adders in Wallace tree structure, with respect to hardware, critical path and power consumption. The Multiplexer logic is used to convert the 63-Bit Thermometer code into 6-Bit Binary code. Also integrated a on chip micro controller calibration, is used to monitor and compensate the nominal nonlinearity of the fine VGA and the resistor ladder. The ADC with 400mV of full scale voltage consumes 15-30 m W of power approximately from a 0.9V supply.
Keywords: 10G Ethernet, Digitally programmable resistor array, A/D conversion, Metastability errors, Wallace tree decoder, Multiplexer based decoder, Short critical path
Edition: Volume 3 Issue 10, October 2014
Pages: 643 - 647
How to Cite this Article?
N. Bharat Kumar Reddy, Sri D. Sharath Babu Rao, "6-Bit Flash ADC for High speed Applications", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT14119, Volume 3 Issue 10, October 2014, 643 - 647
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