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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014
High Speed Vedic Multiplier for 16 Bits Numbers
M. Narasimharao, R. V. Shashanka
Abstract: - Speed and occupational area are key in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors). Knowing that most of the operations involved in processing signal are multiplications since fundamental process in communication modula
Keywords: Compressor, array, Booths multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics
Edition: Volume 3 Issue 11, November 2014,
Pages: 1672 - 1676
How to Cite this Article?
M. Narasimharao, R. V. Shashanka, "High Speed Vedic Multiplier for 16 Bits Numbers", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=OCT141099, Volume 3 Issue 11, November 2014, 1672 - 1676
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