High Speed Vedic Multiplier for 16 Bits Numbers
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Views: 153 , Downloads: 114 | CTR: 75 % | Weekly Popularity: ⮙3

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014

High Speed Vedic Multiplier for 16 Bits Numbers

M. Narasimharao, R. V. Shashanka

- Speed and occupational area are key in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors). Knowing that most of the operations involved in processing signal are multiplications since fundamental process in communication modula

Keywords: Compressor, array, Booths multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics

Edition: Volume 3 Issue 11, November 2014

Pages: 1672 - 1676

Share this Article

How to Cite this Article?

M. Narasimharao, R. V. Shashanka, "High Speed Vedic Multiplier for 16 Bits Numbers", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT141099, Volume 3 Issue 11, November 2014, 1672 - 1676

153 PDF Views | 114 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Compressor'

Views: 141 , Downloads: 104 | CTR: 74 % | Weekly Popularity: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1527 - 1531

Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors

Deepak Kurmi, V. B. Baru

Share this Article

Views: 122 , Downloads: 104 | CTR: 85 % | Weekly Popularity: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2433 - 2438

A Novel Design of Low Power 4:2 Compressor using Adiabatic Logic

Shaswat Singh Bhardwaj, Vishal Moyal

Share this Article

Views: 125 , Downloads: 105 | CTR: 84 % | Weekly Popularity: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Share this Article

Views: 128 , Downloads: 108 | CTR: 84 % | Weekly Popularity: ⮙3

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 1069 - 1074

Design for Low Power Multiplier Based On Fixed Width Replica Redundancy Block & Compressor Trees

Mariya Stephen, Vrinda

Share this Article

Views: 130 , Downloads: 112 | CTR: 86 % | Weekly Popularity: ⮙2

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 3, March 2016

Pages: 1070 - 1072

Design of the Add Multiply Operator Using Modified Booth Recorder

Sruthikeerthana V. M., Pavithra.S

Share this Article

Similar Articles with Keyword 'array'

Views: 121 , Downloads: 95 | CTR: 79 % | Weekly Popularity: ⮙4

Research Paper, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 267 - 270

Self Powered Nanopiezoelectric Device Based on ZnO Nanorod Array on Flexible Conjugated Copolymer Hybrid

Elsa Sneha Thomas

Share this Article

Views: 123 , Downloads: 98 | CTR: 80 % | Weekly Popularity: ⮙1

Research Paper, Electronics & Communication Engineering, Sudan, Volume 3 Issue 7, July 2014

Pages: 1756 - 1759

Verification of a Readout Design for Multiple Energy Discrimination working in Single Photon Processing Pixel Array

Suliman Abdalla, Bengt Oelmman, Amin Babiker

Share this Article

Views: 173 , Downloads: 100 | CTR: 58 % | Weekly Popularity: ⮙5

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this Article

Views: 124 , Downloads: 100 | CTR: 81 % | Weekly Popularity: ⮙3

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 910 - 914

Enhanced Way Tagged Cache Design Using Partial Tag Bloom Filter for Low Level (L2) Cache

Shaima Ibrahim, Sumi Babu

Share this Article

Views: 135 , Downloads: 101 | CTR: 75 % | Weekly Popularity: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2468 - 2472

VHDL Implementation for Adaptive FIR filter and its Novel Application using Systolic Architecture

Ghanshyam A. Chune, Vijay Bagdi

Share this Article

Similar Articles with Keyword 'Booths multiplier'

Views: 176 , Downloads: 110 | CTR: 63 % | Weekly Popularity: ⮙3

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 7, July 2013

Pages: 264 - 267

Implementation of an Arithmetic Logic Unit using Area Efficient Carry Look-Ahead Adder and Booths Multiplier

Sarwagya Chaudhary

Share this Article

Views: 153 , Downloads: 114 | CTR: 75 % | Weekly Popularity: ⮙3

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1672 - 1676

High Speed Vedic Multiplier for 16 Bits Numbers

M. Narasimharao, R. V. Shashanka

Share this Article

Similar Articles with Keyword 'Vedic Mathematics'

Views: 84 , Downloads: 59 | CTR: 70 % | Weekly Popularity: ⮙2

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article

Views: 130 , Downloads: 101 | CTR: 78 %

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3221 - 3230

Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics

Shahina M. Salim, Sonal A. Lakhotiya

Share this Article

Views: 141 , Downloads: 104 | CTR: 74 % | Weekly Popularity: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1527 - 1531

Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors

Deepak Kurmi, V. B. Baru

Share this Article

Views: 136 , Downloads: 111 | CTR: 82 % | Weekly Popularity: ⮙1

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 1720 - 1722

High Speed Convolution and Deconvolution Algorithm based on Ancient Indian Vedic Mathematics

Priya Lad, Dr. A. A.Gurjar

Share this Article

Views: 141 , Downloads: 113 | CTR: 80 % | Weekly Popularity: ⮙4

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1321 - 1324

A Hierarchical Design of 32-bit Vedic Multiplier

Arpita S. Likhitkar, M. N. Thakare, S. R. Vaidya

Share this Article
Top