M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014
High Speed Vedic Multiplier for 16 Bits Numbers
M. Narasimharao, R. V. Shashanka
- Speed and occupational area are key in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors). Knowing that most of the operations involved in processing signal are multiplications since fundamental process in communication modula
Keywords: Compressor, array, Booths multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics
Edition: Volume 3 Issue 11, November 2014
Pages: 1672 - 1676
How to Cite this Article?
M. Narasimharao, R. V. Shashanka, "High Speed Vedic Multiplier for 16 Bits Numbers", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT141099, Volume 3 Issue 11, November 2014, 1672 - 1676
Similar Articles with Keyword 'Compressor'
Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors
Deepak Kurmi, V. B. Baru
A Novel Design of Low Power 4:2 Compressor using Adiabatic Logic
Shaswat Singh Bhardwaj, Vishal Moyal
Similar Articles with Keyword 'array'
Design of Efficient Braun Multiplier for Arithmetic Applications
Self Powered Nanopiezoelectric Device Based on ZnO Nanorod Array on Flexible Conjugated Copolymer Hybrid
Elsa Sneha Thomas
Similar Articles with Keyword 'Vedic Mathematics'
Renovated 32 Bit ALU Using Hybrid Techniques
Manju Davis, Uma N
Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics
Shahina M. Salim, Sonal A. Lakhotiya