High Speed Vedic Multiplier for 16 Bits Numbers
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014

High Speed Vedic Multiplier for 16 Bits Numbers

M. Narasimharao, R. V. Shashanka

- Speed and occupational area are key in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors). Knowing that most of the operations involved in processing signal are multiplications since fundamental process in communication modula

Keywords: Compressor, array, Booths multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics

Edition: Volume 3 Issue 11, November 2014

Pages: 1672 - 1676

Share this Article

How to Cite this Article?

M. Narasimharao, R. V. Shashanka, "High Speed Vedic Multiplier for 16 Bits Numbers", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT141099, Volume 3 Issue 11, November 2014, 1672 - 1676

112 PDF Views | 84 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Compressor'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 1069 - 1074

Design for Low Power Multiplier Based On Fixed Width Replica Redundancy Block & Compressor Trees

Mariya Stephen, Vrinda

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2433 - 2438

A Novel Design of Low Power 4:2 Compressor using Adiabatic Logic

Shaswat Singh Bhardwaj, Vishal Moyal

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1672 - 1676

High Speed Vedic Multiplier for 16 Bits Numbers

M. Narasimharao, R. V. Shashanka

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1527 - 1531

Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors

Deepak Kurmi, V. B. Baru

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Share this Article

Similar Articles with Keyword 'array'

Research Paper, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 267 - 270

Self Powered Nanopiezoelectric Device Based on ZnO Nanorod Array on Flexible Conjugated Copolymer Hybrid

Elsa Sneha Thomas

Share this Article

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 2745 - 2749

An Efficient Low Latency Low Complexity Architecture for Matching of Information Coded with Error?Correcting Codes

Sankareswari.M, Udhayakumar.S

Share this Article

Research Paper, Electronics & Communication Engineering, Sudan, Volume 3 Issue 7, July 2014

Pages: 1756 - 1759

Verification of a Readout Design for Multiple Energy Discrimination working in Single Photon Processing Pixel Array

Suliman Abdalla, Bengt Oelmman, Amin Babiker

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2430 - 2432

Development of Low Cost Smart Antenna System and its FPGA Implementation

Harshveer Singh Grewal, Paramveer Singh Gill

Share this Article

Similar Articles with Keyword 'Booths multiplier'

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 7, July 2013

Pages: 264 - 267

Implementation of an Arithmetic Logic Unit using Area Efficient Carry Look-Ahead Adder and Booths Multiplier

Sarwagya Chaudhary

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1672 - 1676

High Speed Vedic Multiplier for 16 Bits Numbers

M. Narasimharao, R. V. Shashanka

Share this Article

Similar Articles with Keyword 'Vedic Mathematics'

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3221 - 3230

Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics

Shahina M. Salim, Sonal A. Lakhotiya

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1672 - 1676

High Speed Vedic Multiplier for 16 Bits Numbers

M. Narasimharao, R. V. Shashanka

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1527 - 1531

Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors

Deepak Kurmi, V. B. Baru

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1321 - 1324

A Hierarchical Design of 32-bit Vedic Multiplier

Arpita S. Likhitkar, M. N. Thakare, S. R. Vaidya

Share this Article
Top