Design and Analysis of f2g Gate using Adiabatic Technique
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 6, June 2016

Design and Analysis of f2g Gate using Adiabatic Technique

Renganayaki.G, Thiyagu.P

This paper presents the comparison of conventional and two efficient adiabatic logics ECRL and PFAL. F2G gate is implemented using these two design technique. F2G gates are reversible gates. Reversible computing performed on F2G gates with adiabatic design techniques promises more reduced in power consumption as compared to traditional adiabatic CMOS circuits. Comparison in this paper shows very encouraging results in terms of average power consumption, transistor count. The designs are simulated and implemented on Cadence ICE6.1.5 virtuoso Design Environment using UMC 180 nm transistor model. The simulation results indicate that ECRL is better than PFAL, adiabatic logic at lower value load capacitancein terms of average power consumption and transistor count for implementation of F2G gates at low frequency andlow power application.

Keywords: ECRL, PFAL, CMOS Adiabatic Logic, F2G Gates, REVERSIBLE LOGIC

Edition: Volume 5 Issue 6, June 2016

Pages: 2363 - 2367

Share this Article

How to Cite this Article?

Renganayaki.G, Thiyagu.P, "Design and Analysis of f2g Gate using Adiabatic Technique", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV164818, Volume 5 Issue 6, June 2016, 2363 - 2367

102 PDF Views | 99 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'ECRL'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1409 - 1413

Design and Analysis of Asynchronous 16*16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic

C. S. Harmya Sreeja, N. Sri Krishna Yadav

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 6, June 2016

Pages: 2363 - 2367

Design and Analysis of f2g Gate using Adiabatic Technique

Renganayaki.G, Thiyagu.P

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 43 - 45

Low Power Circuit Design Using Positive Feedback Adiabatic Logic

Arjun Mishra, Neha Singh

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015

Pages: 258 - 263

Carry Select Adder Implementation using Asynchronous Fine Grain Power Gated Logic

Nadisha E B, Akhila P R

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 6, June 2016

Pages: 1270 - 1274

Design and Analysis of Full Adder Using Adiabatic Logic

Durgesh Patel, Dr. S. R. P. Sinha

Share this Article

Similar Articles with Keyword 'PFAL'

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1214 - 1218

Review on Different Types of Power Efficient Adiabatic Logics

Vijendra Pratap Singh, Dr. S.R.P Sinha

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 6, June 2016

Pages: 2363 - 2367

Design and Analysis of f2g Gate using Adiabatic Technique

Renganayaki.G, Thiyagu.P

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 9, September 2016

Pages: 1554 - 1558

Ultra Low Power Design of Combinational Logic Circuits

M. Shyam Sundar

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 43 - 45

Low Power Circuit Design Using Positive Feedback Adiabatic Logic

Arjun Mishra, Neha Singh

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 6, June 2016

Pages: 1270 - 1274

Design and Analysis of Full Adder Using Adiabatic Logic

Durgesh Patel, Dr. S. R. P. Sinha

Share this Article

Similar Articles with Keyword 'REVERSIBLE LOGIC'

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 10, October 2014

Pages: 2286 - 2288

A Review on Reversible Logic Gate Multipliers

Supreetha Rao, Supreetha M, Vidya Venkatesh, Prajna

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2433 - 2438

A Novel Design of Low Power 4:2 Compressor using Adiabatic Logic

Shaswat Singh Bhardwaj, Vishal Moyal

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2218 - 2222

A Power Efficient Design of Reversible RAM Using Pseudo Reed-Muller Expression

Shibinu A. R, Rajkumar.P

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 12, December 2014

Pages: 1100 - 1102

Design and Implementation BCD adder Using Integrated Qubit Gates for Quantum Applications

G. Sivakrishna, K. Amarnath, S. Madhava Rao

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 901 - 904

Low Power 8 Bit quantum ALU Implementation Using Reversible Logic Structure

Vijay G. Roy, P. R. Indurkar, D. M. Khatri

Share this Article
Top