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Survey Paper | Electronics & Communication Engineering | India | Volume 5 Issue 6, June 2016

A Brief Review on Soft Errors and LDPC Codes

Prashant Puri Goswami ^[6] | Pankaj M Gulhane ^[3]

Abstract: In current scenario, due to high demand of technology scaling and higher integration density, the designers are using nanodevices for computer system and other memory system. Despite having many advantages such as lower area overhead and lower power consumption, these devices has major disadvantage that they are more prone to soft errors. Due to this reason the reliability of these systems are severely affected. Many error detection and correction codes have been studied to reduce this error. There are vast classes of such codes, some of them are hamming codes, turbo codes, BCH codes and LDPC codes. But among these codes LDPC codes achieve better performance and lower decoding complexity. LDPC codes were originally discovered by Robert G. Gallager. But after the rediscovery of LDPC codes by Mackay and Neal in 1995 interest on LDPC codes increases because of its bit error performance approaches asymptotically the Shannon limit. An LDPC code is a special class of linear block codes whose parity-check matrix H has low density of ones i. e. sparse. Due to this sparsity in LDPC codes there is low complexity decoding and its implementation is also simple. Also LDPC codes provides large degree of parallelism that can be exploited in the decoder and in LDPC codes information block length are long enough. In addition LDPC codes provides wide range of trade-offs between performance and complexity. LDPC codes find its application in many areas such as satellite transmission of digital television. LDPC codes are also used for 10GBase-T Ethernet that transmits data at 10 gigabits per second over twisted pair cable.

Keywords: LDPC, EG-LDPC, FSD, BER, MBU

Edition: Volume 5 Issue 6, June 2016,

Pages: 662 - 665

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