Design and Analysis of Full Adder Using Adiabatic Logic
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 6, June 2016

Design and Analysis of Full Adder Using Adiabatic Logic

Durgesh Patel, Dr. S. R. P. Sinha

Power dissipation is an increasing concern in VLSI circuits. New logic circuits have been developed to meet these power requirements. Power dissipation can be minimized by using various adiabatic logic circuits. In this paper an Adder circuit has been proposed based on 2PASCL and ECRL logic and then compared with Positive Feedback Adiabatic Logic (PFAL), Two-Phase Adiabatic Static Clocked Logic (2PASCL) respectively. Comparison shows significant power saving.

Keywords: adiabatic switching, energy dissipation, power clock, 2PASCL, ECRL

Edition: Volume 5 Issue 6, June 2016

Pages: 1270 - 1274

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How to Cite this Article?

Durgesh Patel, Dr. S. R. P. Sinha, "Design and Analysis of Full Adder Using Adiabatic Logic", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV164027, Volume 5 Issue 6, June 2016, 1270 - 1274

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