International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064



M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 5, May 2016

Realization of Programmable PRPG with Enhanced Fault Coverage Gradient

Lakshmi Asokan, Jeena Maria Cherian

This paper describes a low power programmable pseudorandom pattern generator with desired toggling level and also enhanced fault coverage compared with other BIST based on PRPG. It comprised of finite state machine LFSR driving a phase shifter and it allows the device to produce binary sequence with preselected toggling activity. Generator is automatically controlled providing easy and precise tuning. Furthermore, this paper introduces a test compression method to avoid repeated pattern generation for testing the same device. The main highlight of this paper is to reduce the test data volume and test data memory.

Keywords: BIST, low power test, PRPG, test data volume compression

Edition: Volume 5 Issue 5, May 2016

Pages: 2286 - 2288


How to Cite this Article?

Lakshmi Asokan, Jeena Maria Cherian, "Realization of Programmable PRPG with Enhanced Fault Coverage Gradient", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV163979, Volume 5 Issue 5, May 2016, 2286 - 2288

32 PDF Views | 27 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'BIST'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 5, May 2016

Pages: 2286 - 2288

Realization of Programmable PRPG with Enhanced Fault Coverage Gradient

Lakshmi Asokan, Jeena Maria Cherian

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 563 - 567

VLSI Implementation of Parallel Prefix Subtractor using Modified 2?s Complement Technique and BIST Verification using LFSR Technique

Malti Kumari, Vipin Gupta, Gaurav K Jindal

Share this article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 1294 - 1297

Weighted Random Pattern Generator by Using BIST

Rajni Gajendra, Rahul Gedam

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 449 - 453

Design of Microprocessor Hardware Self-Test Unit on FPGA

Savitha Kamble

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 9, September 2013

Pages: 119 - 123

Concurrent Online Test of RFID Memories Using MBIST

Jyothi Rani Degala, Kota Nageswara Rao

Share this article



Similar Articles with Keyword 'low power test'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 5, May 2016

Pages: 2286 - 2288

Realization of Programmable PRPG with Enhanced Fault Coverage Gradient

Lakshmi Asokan, Jeena Maria Cherian

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 159 - 164

Analysis of Low Power Test Pattern Generator by Using Low Power Linear Feedback Shift Register (LP-LFSR)

Nelli Shireesha, Katakam Divya

Share this article
Top