M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 5, May 2016
Design and Analysis of Low Power High Speed Hybrid Alternative Full Adder Circuits
Shreedevi | Taranath H. B
Abstract: This project deals with designs of 1-bit hybrid alternative full adder using complementary metal-oxide-semiconductor (CMOS) logic, gate diffusion input (GDI) technique, modified GDI and transmission gate logic are reported. These designs are implemented using Mentor graphics tool. The power dissipation and transistor count is compared to the other hybrid adder designs and the existing designs such as complementary pass-transistor logic, transmission gate adder and hybrid pass-logic with static CMOS output drive full adder, mixed topology of GDI (Gate diffusion Input) technique with both inverter and mirror adder so on. This design is divided into three modules and found to working efficiently with less power dissipation and transistor count at 180nm technology.
Keywords: CMOS, hybrid adder, GDI full adder, low power, transistor count and adders
Edition: Volume 5 Issue 5, May 2016,
Pages: 902 - 907
How to Cite this Article?
Shreedevi, Taranath H. B, "Design and Analysis of Low Power High Speed Hybrid Alternative Full Adder Circuits", International Journal of Science and Research (IJSR), Volume 5 Issue 5, May 2016, pp. 902-907, https://www.ijsr.net/get_abstract.php?paper_id=NOV163491
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