A Review: FPGA Implementation of Reconfigurable Digital FIR Filter
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Review Papers | Electronics & Communication Engineering | India | Volume 5 Issue 3, March 2016

A Review: FPGA Implementation of Reconfigurable Digital FIR Filter

Pradnya D. Shahare, Samrat S. Thorat

This brief presents, the different methods namely conversion based approaches and memory based methods for implementation of FIR filter. It also presents an efficient implementation of Finite Impulse Response Filter (FIR) using Distributed Arithmetic (DA) architecture. The distributed arithmetic is an area efficient technique of FIR filter implementation. The existing methods have used MAC units, which need more hardware, area and power. The multipliers in FIR filter are replaced with multiplier less DA based technique. The DA based technique consists of Look Up Table (LUT), shift registers and scaling accumulator. Replacing MAC with LUT-Based DA algorithm is having power, efficiency and less area usage. With the reduction of hardware in terms of multipliers, our goal is to reduce the parameters namely, hardware, area and power.

Keywords: RAM based LUT, Distributed Arithmetic, Conversion based approach, Field Programmable Gate Array, FIR Filter

Edition: Volume 5 Issue 3, March 2016

Pages: 539 - 542

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How to Cite this Article?

Pradnya D. Shahare, Samrat S. Thorat, "A Review: FPGA Implementation of Reconfigurable Digital FIR Filter", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV161872, Volume 5 Issue 3, March 2016, 539 - 542

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