International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064



Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 12, December 2015

Design and Implementation of 8 BIT Vedic Multipliers USING HNG Gates

Illa Bharti, Manisha Waje

Now a days, reversible logics are emerging field in VLSI design in which Energy dissipation is an important consideration. Reversible logic is first related to energy. Researcher like Landauer states that information loss due to function irreversibility leads to energy dissipation. Thus reversibility will become an essential feature in future electronics circuit design. Reversible circuits are of high interest in applications like DSPs, low power CMOS design, nanotechnology, optical computing and quantum computing etc. The main aim and purpose of this paper is to improve the speed and power dissipation of the processor by using efficient Vedic multiplier. Vedic multiplier known as Urdhva Tiryakbhayam which means vertical and crosswise in English. This multiplier is designed and implemented using reversible logic Feynman Gate, Peres Gate and HNG gate. Feynman and Peres gates are used to implement the basic two bit multipliers and HNG gate is used as full adder for summation of the partial product generated by two bit multipliers in four bit multiplier. 8*8 bit multiplier is designed using four bit multipliers and three eight bit ripple carry adders. The proposed system is designed using VHDL and implemented through Xilinx ISE 13.2 Navigator

Keywords: Vedic multiplier, Urdhva Tiryakbhayam, Reversible logic gates, Garbage outputs, Constant outputs, Xilinx Sparta 3E FPGA kit

Edition: Volume 4 Issue 12, December 2015

Pages: 2143 - 2148


How to Cite this Article?

Illa Bharti, Manisha Waje, "Design and Implementation of 8 BIT Vedic Multipliers USING HNG Gates", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV152520, Volume 4 Issue 12, December 2015, 2143 - 2148

27 PDF Views | 26 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Vedic multiplier'

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1527 - 1531

Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors

Deepak Kurmi, V. B. Baru

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1672 - 1676

High Speed Vedic Multiplier for 16 Bits Numbers

M. Narasimharao, R. V. Shashanka

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 2143 - 2148

Design and Implementation of 8 BIT Vedic Multipliers USING HNG Gates

Illa Bharti, Manisha Waje

Share this article

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1169 - 1173

A New Architecture of High Performance WG Stream Cipher

Grace Mary S., Abhila R. Krishna

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1843 - 1847

Design of 8 x 8 Vedic Multiplier using Quaternary-Logic & Pipelining Architecture

Vivek D. Wanjari, Prof. R. N. Mandavgane, Prof. Shailesh Sakhare

Share this article



Similar Articles with Keyword 'Reversible logic gates'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 901 - 904

Low Power 8 Bit quantum ALU Implementation Using Reversible Logic Structure

Vijay G. Roy, P. R. Indurkar, D. M. Khatri

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 2143 - 2148

Design and Implementation of 8 BIT Vedic Multipliers USING HNG Gates

Illa Bharti, Manisha Waje

Share this article



Similar Articles with Keyword 'Garbage outputs'

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 2143 - 2148

Design and Implementation of 8 BIT Vedic Multipliers USING HNG Gates

Illa Bharti, Manisha Waje

Share this article

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 10, October 2014

Pages: 2286 - 2288

A Review on Reversible Logic Gate Multipliers

Supreetha Rao, Supreetha M, Vidya Venkatesh, Prajna

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 64 - 68

Design and Implementation of Ternary Bidirectional Barrel Shifter Using Multi-Valued Reversible Logic

Sunil Thomas Paul, M. Rajmohan

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 12, December 2014

Pages: 1100 - 1102

Design and Implementation BCD adder Using Integrated Qubit Gates for Quantum Applications

G. Sivakrishna, K. Amarnath, S. Madhava Rao

Share this article
Top