Design and Simulation of NOT and NAND Gate Using Hybrid SET-MOS Technology
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 12, December 2015

Design and Simulation of NOT and NAND Gate Using Hybrid SET-MOS Technology

Daya Nand Gupta, S. R. P. Sinha

Single Electron Transistor (SET) is an advanced technology for future low power VLSI devices. SET has high integration density and a low power consumption device. While building logic circuits that comprise only of SETs, it is observed that the gate voltage at the input must be higher than the power supply of SET for better switching characteristics. This limitation of SET in the power and gate supply voltages makes it practically inappropriate to build circuits. An approach to overcome this problem, hybridization of SET and CMOS transistor is implemented. In this paper, different types of hybrid SET-MOS circuits are designed such as hybrid SET-MOS inverter and NAND gate is designed and implemented. All the circuits are verified by means of PSpice simulation software version 16.5

Keywords: Single Electron Transistor SET, Coulomb Blockade, Orthodox Theory, Hybrid SET-MOS, Pspice

Edition: Volume 4 Issue 12, December 2015

Pages: 2270 - 2274

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How to Cite this Article?

Daya Nand Gupta, S. R. P. Sinha, "Design and Simulation of NOT and NAND Gate Using Hybrid SET-MOS Technology", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV152487, Volume 4 Issue 12, December 2015, 2270 - 2274

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