Design and Analysis of Dynamic Current Mode Full Adder with reduced Power and Delay
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 11, November 2015

Design and Analysis of Dynamic Current Mode Full Adder with reduced Power and Delay

Dr. S.R.P. Sinha, Namita Tiwari

Current mode logic (CML) technology is popular as it offers high performance with very low power dissipation, equal charging and discharging times, equal noise margins and low output logic swing, therefore high-speed performance is achieved. In this paper, MOS current mode logic (MCML), dynamic current mode logic (DyCML) and cascaded dynamic current mode logic techniques are analyzed and applied to the generation of digital arithmetic circuits. Based on the presented analysis a new current mode full adder is proposed where the circuit of Dynamic Current mode full adder is modified. It is shown that in the proposed full adder circuit both the power consumption and delay time are reduced. The circuits are simulated using TANNER tool with 0.18m technology and supply voltage 1.5V.

Keywords: MOS current mode logic, Power dissipation, Output voltage swing Dynamic poer consumption, Self timed buffer

Edition: Volume 4 Issue 11, November 2015

Pages: 2383 - 2388

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How to Cite this Article?

Dr. S.R.P. Sinha, Namita Tiwari, "Design and Analysis of Dynamic Current Mode Full Adder with reduced Power and Delay", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV151617, Volume 4 Issue 11, November 2015, 2383 - 2388

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