Design and Analysis of Dynamic Comparator with Reduced Power and Delay
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 11, November 2015

Design and Analysis of Dynamic Comparator with Reduced Power and Delay

Shashank Shekhar, Dr. S. R. P. Sinha

The need for low-power and high speed analog-to-digital converters is pushing toward the use of dynamic comparators to maximize speed and power efficiency. In this paper, performances of various types of the dynamic comparators are being compared in terms of speed, delay and power. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional comparator is modified for low-power and fast operation even in small supply voltages. It is shown that in the proposed dynamic comparator both the power consumption and delay time are reduced. The circuits are simulated using TANNER tool with 0.18m technology and supply voltage 1.8V.

Keywords: Preamplifier, Kickback noise, Dynamic Latch Comparator, Transmission Gate, Parasitic Node Capacitance

Edition: Volume 4 Issue 11, November 2015

Pages: 1025 - 1029

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Shashank Shekhar, Dr. S. R. P. Sinha, "Design and Analysis of Dynamic Comparator with Reduced Power and Delay", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV151349, Volume 4 Issue 11, November 2015, 1025 - 1029

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