Carry Select Adder Implementation using Asynchronous Fine Grain Power Gated Logic
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 11, November 2015

Carry Select Adder Implementation using Asynchronous Fine Grain Power Gated Logic

Nadisha E B, Akhila P R

This paper presents a low power logic family, called asynchronous fine-grain power-gated logic (AFPL). Each pipeline stage is comprised of the logic function called efficient charge recovery logic (ECRL) gatesand a handshake controller. ECRL gates have negligible leakage power dissipation. By incorporatingpartial charge reuse (PCR) mechanism the energy dissipation required to complete the evaluation of an ECRL gate can be reduced. Moreover, AFPL-PCR adopts a C*-element, in its handshake controllers. To mitigate the hardware overhead of the AFPL circuit, circuit simplificationtechniques have been developed.

Keywords: AFPL circuits, CSLA adders, PCR mechanism, ECRL logic gates

Edition: Volume 4 Issue 11, November 2015

Pages: 258 - 263

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How to Cite this Article?

Nadisha E B, Akhila P R, "Carry Select Adder Implementation using Asynchronous Fine Grain Power Gated Logic", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=NOV151041, Volume 4 Issue 11, November 2015, 258 - 263

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