Design of IEEE - 754 Floating point Arithmetic Processor
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 3, March 2013

Design of IEEE - 754 Floating point Arithmetic Processor

J. Laxmi, R. Ramprakash

In this paper, we deal with the designing of a 32-bit floating point arithmetic processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating point operations are incorporated into the design as functions. The logic for these is different from the ordinary arithmetic functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operations are conducted on them. The floating point representation for a standard single precision number is a 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponent, the next seven bits are that of the exponent magnitude, and the remaining 24 bits represent the mantissa sign. The exponent in this IEEE standard is represented in excess-127 format all the arithmetic functions like addition, subtraction, multiplication and division will be design by the processor. The main functional blocks of floating point arithmetic processor design includes, Arithmetic logic unit(ALU), Register organization, control & decoding unit, memory block, 32-bit floating point addition, subtraction, multiplication and division blocks. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The overall system architecture will be designed using HDL language and simulation, synthesis.

Keywords: single, dual precision, floating point, ALU, FPGA

Edition: Volume 2 Issue 3, March 2013

Pages: 190 - 193

Share this Article

How to Cite this Article?

J. Laxmi, R. Ramprakash, "Design of IEEE - 754 Floating point Arithmetic Processor", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=IJSRON2013560, Volume 2 Issue 3, March 2013, 190 - 193

122 PDF Views | 114 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'single'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014

Pages: 481 - 483

Communication of Multi Mobile-Robots Based On ZigBee Network

Taskeen Sultana, Zeenath

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 267 - 270

Self Powered Nanopiezoelectric Device Based on ZnO Nanorod Array on Flexible Conjugated Copolymer Hybrid

Elsa Sneha Thomas

Share this Article

Research Paper, Electronics & Communication Engineering, Sudan, Volume 3 Issue 7, July 2014

Pages: 1756 - 1759

Verification of a Readout Design for Multiple Energy Discrimination working in Single Photon Processing Pixel Array

Suliman Abdalla, Bengt Oelmman, Amin Babiker

Share this Article

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 5, May 2014

Pages: 1141 - 1145

A Review Based on Effects of Change in Thickness and Number of Layers on Microwave Absorbing Materials

Harsroop Kaur, Gagan Deep Aul

Share this Article

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this Article

Similar Articles with Keyword 'floating point'

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1378 - 1381

Design and Analysis of Double Precision Floating Point Division Operator Based on CORDIC Algorithm

Chetan Dudhagave, Hari Krishna Moorthy

Share this Article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 1847 - 1851

Review on Floating Point Adder and Converter Units Using VHDL

Abhishek Kumar, Mayur S. Dhait

Share this Article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 169 - 171

A Review: Design and Simulation of Binary Floating Point Multiplier Using VHDL

Ujjwala V. Chaudhari, Prof A. P. Dhande

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015

Pages: 344 - 347

Area Optimized Double Precision IEEE Floating Point Adder

Elizabeth Joseph Mattam, Deepa Balakrishnan

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 3, March 2013

Pages: 80 - 83

VLSI Implementation of H.264 Transform and Quantization Algorithms

G. Dileepvamshi, P. Ramakrishna

Share this Article

Similar Articles with Keyword 'ALU'

Research Paper, Electronics & Communication Engineering, India, Volume 7 Issue 6, June 2018

Pages: 1662 - 1664

Enhancement of Gray Level Image by Fuzzy and Filter Technique

Monalisa Pandey, Pankaj Sharma

Share this Article

Survey Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 1067 - 1069

A Secure Text (Missile Co-ordinate) Transmission Using Digital Watermarking

Jagtap. D. V, M. D. Patil

Share this Article

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 2276 - 2281

Skin based Data hiding in Images by Using Haar and db2 DWT Techniques

Swapnali Zagade, Smita Bhosale

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 7, July 2013

Pages: 264 - 267

Implementation of an Arithmetic Logic Unit using Area Efficient Carry Look-Ahead Adder and Booths Multiplier

Sarwagya Chaudhary

Share this Article

Similar Articles with Keyword 'FPGA'

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 11, November 2016

Pages: 422 - 426

An Segmentation Under Connected Components Based on Watershed Algorithm Using FPGA Processor

R. Kiruthikaa, S. Salaiselvapathy

Share this Article

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 878 - 884

ASIC Architectures for Implementing ECC Arithmetic over Finite Fields

Hemanth Ravindra, Jalaja S

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1515 - 1518

FPGA based Underwater System for Ultrasound Communication

Pooja Sabale, S.T. Khot

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3033 - 3036

FIR Interpolation Filter for Multi-Standard Digital Up Converter Using FPGA

Chaithra M. R., Yashwanth N

Share this Article
Top